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Design Engineering
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153643 Requisition #
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Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

    Job Description: 
    As the Physical design lead of the MPSoC design team in Hyderabad,  you'll be responsible for leading timing closure and synthesis for complex SOC designs. Taking design RTL team, meeting synthesis targets and validating pre-layout and post route timing analysis and signoff will be primary responsibilities
     
     
     Essential Duties , Competencies & Responsibilities include, but not limited to: 
     
    • Hands on ownership of one or more activities -synthesis, timing constraints development, STA signoff.
    • Interacting with RTL design teams to resolve all implementation issues
    • Exercises solid analytical problem solving in troubleshooting component designs (e.g., timing analysis, constraint setting)
    • Generate quality metrics and checklists for design closure and tapeout reviews
    • Develop or enhance scripts for various physical closure activities
    • Accurately documents and effectively communicates the rational for a design to design implementation stakeholders (e.g., peers, Technical Solution Groups, management)
    • Holds peer reviews of designs or methodologies to accommodate corrections, changing requirements, or new features
    • Coordinates with and manages external vendor deliverables

    Job Requirements: 

    • Good understanding of complete physical design flow in 28nm, 16nm and below
    • Hands on experience in  timing report analysis, SDC constraint creation, verification debug, DMSA timing ECO generation,  
    • Expertise with Synthesis and STA tools ( DC an primetime)is a must
    • Strong scripting and automation skills using Perl, TCL, C-shell, Make and/or other scripting languages.
    • Experience in quality check tools is a plus - Fishtail, CDC 0-in,
    • Must have gone through multiple tapeout cycles, revisions and metal ECOs
    • Strong verbal and written communication skills.
    Education Requirements : MSEE / BE

    Years of Experience : 6+

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