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Design Engineering
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153396 Requisition #
Thanks for your interest in the Staff Design Engineer position. Unfortunately this position has been closed but you can search our 233 open jobs by clicking here.

 

  • Requires BS w/ 7+ years or MS w/ 5+ years or PhD w/ 3+ years in Electrical Engineering, Computer Engineering, or Computer Science.
  • Requires proven track record in technical leadership and mentoring. This includes planning, execution, tracking, verification closure, and delivery to programs.
  • Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.
  • Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
  • Verification experience in  DSP, ADC/DAC, Gigabit Transceivers, AXI, HBM, DDR4, PCIe verification is a plus.
  • Requires strong experience in full chip verification.
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
  • Strong understanding of different phases of ASIC and/or full custom chip development is required.
  • Experience in modeling SystemC and using SystemC based models in verification is a plus.
  • Experience with FPGA programming and software is a plus.
  • Verification experience in  PCIe, Processors, Graphics is a plus.
  • Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
  • Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.

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