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Design Verification Engineer

📁
Design Engineering
📅
155250 Requisition #
Thanks for your interest in the Design Verification Engineer position. Unfortunately this position has been closed but you can search our 238 open jobs by clicking here.
Requirements:
Candidate is expected to be a strong team player with good communication skills and one who is capable to work independently with an eye towards improving overall product quality.
  • Requires BS/BTech w/ 2 yrs or MS in Electrical Engineering, Computer Engineering or Computer Science.
  • Understanding of state of the art digital design and verification techniques, including simulation-based verification flow, assertion and metric-driven verification.
  • Proficiency in System Verilog and UVM.
  • Proficiency in C, Perl, Python and/or other scripting language.
  • Familiarity with verification management tools and understanding of database management particularly as it pertains to regression management.
  • Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, or Cadence IES is a strong plus.
  • Basic understanding of formal property checking, gate level simulation, power verification using UPF, reset verification, and/or contention checking is a plus.

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