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Physical Design/Implementation Engineer, ASIC

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Design Engineering
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155317 Requisition #
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  • The candidate will perform Netlist to GDS implementation of digital designs
  • The candidate will be responsible for completion of tasks that include floor planning and partitioning, synthesis, formal verification, place and route, clock tree synthesis, signal integrity analysis and timing closure.
  • Develop and implement plans to synthesize, implement including Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block level (100K to 1M+ gates) which are coded in VHDL/Verilog
  • Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies
  • Extensive experience in static timing analysis, power and noise analysis and back-end verification across multiple projects
  • Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones
  • Provide/propose new/enhance synthesis, DFT and STA flow and methodology
  • Experience in Design-For-Test tools & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation)
  • Demonstrated proficiency with backend design EDA tools Synopsys or Cadence
  • Experience with Verilog/VHDL and Digital Design Principles
  • Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements
  • Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule
  • Successfully track records of taping out complex SOC in 16nm and beyond
  • Working knowledge of deep sub-micron routing issues as they relate to power and timing
  • Strong scripting skills in Perl, TCL and Shell, particularly in synthesis & timing analysis
  • Document all the back end deliverables
  • Lead the team as the technical advisor and mentor other engineers
  • Self-motivated team worker, good verbal and written communication skills

 


Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs and 3DICs. Xilinx's all-programmable devices are designed into tens of thousands of products that improve the quality of the everyday lives of billions of people worldwide. For over 30 years, Xilinx has been behind some of the greatest advancements in technology and science - from the industry's first fabless semiconductor model to the NASA Curiosity Mars Rover, to today's autonomous vehicles and hyperscale data centers. Xilinx uniquely enables applications that are both software-defined, yet hardware optimized - enabling smart, connected and differentiated applications across technology's biggest megatrends, including Machine Learning, 5G Wireless, Embedded Vision, Industrial IoT and Cloud Computing and more.
If you are a passionate, innovative and an out-of-the-box thinker that enjoys challenging projects, Xilinx is the right place for you. Our global team is growing and we are looking for bold, collaborative, and creative people to help deliver groundbreaking technologies that enable our customers to differentiate. Come do your best work and live your best life through collaboration, wellness and giving back to your community as a member of the ONEXILINX team.

 

 

 

 

 

Education Requirements and Experience

BS degree in Engineering (e.g. Electrical, Mechanical, Industrial, etc) or equivalent practical experience. 
5+ years of experience in ASIC physical design flows and methodologies in 7nm, 16nm and 28nm process nodes. Multiple foundry experience. 
Experience in physical design flows and methodologies (including synthesis, place and route), STA, formal verification, CDC and power analysis using tools such as Design Compiler, ICC/ICC2, Innovus/EDI, Primetime, Conformal, Spyglass and Power Artist. Experience with scripting in TCL, Perl, Python. 
Strong written, verbal and debugging skills. Knowledge of DRAM memory controller design and architecture is a plus

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