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Senior Design Engineer 2

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Design Engineering
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154336 Requisition #
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Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are:

  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless


Detailed Description

This exciting position in the Xilinx IP Engineering group as the high speed link u-architect and lead designer will provide the individual with an opportunity to demonstrate strong technical leadership in Xilinx next generation high speed serial link IP offerings. Join us in delivering innovative IP solutions as we embark on our journey in providing world class high speed link designs running at well over 25Gbs for Xilinx All Programmable FPGA platforms

As a Senior Design Engineer you will work as part of a team responsible for all phases of product development from definition to execution and Productization. Senior Design engineers are expected to participate in and lead all aspects of a technical project including: working closely with Product marketing managers, u-Architecture development for individual IPs or IP subsystems, leading cross-functional IP teams from front-end development through Productization

This position requires the individual to be creative, team-oriented, technology savvy, able to u-architect and lead complex designs given a high level architecture and take complete responsibility for a quality delivery of the designs
Job Requirements

A major part of your responsibility will be to take a lead technical role in all phases of the product development cycle from architecture through implementation, prototyping, validation and support including: 

·        Evaluating high level architecture to a implementation feasibility level
·        Be the main liaison from the IP engineering team to the high speed IO design team and be the local high speed link design expert
·        Contribute to new process improvement in design and development methodologies that impact the productivity 
·        Evaluating and executing design and development plans for IPs 
·        u-Architecture, design, documentation, prototyping 
·        Working with cross functional teams in reviewing the verification and validation plans and ensure the product delivered is of high quality

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Equal Employment Statements

UNITED STATES: Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is used only in compliance with US Federal laws and is not gathered for employment decisions. Responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.

CANADA and EUROPE: Xilinx is an equal opportunities employer.

SINGAPORE and AUSTRALIA: Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to age, race, gender, religion, marital status and family responsibilities, disability or sexual orientation.

CHINA, HONG KONG, KOREA, PHILIPPINES and TAIWAN: Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation.