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Senior Design Engineer 1

📁
Design Engineering
📅
155332 Requisition #
Thanks for your interest in the Senior Design Engineer 1 position. Unfortunately this position has been closed but you can search our 238 open jobs by clicking here.
Your responsibilities include but are not limited to:
 
 
  • Block level place and route to design closure meeting timing, area and power constraints.
  • Develop full chip design methodologies and flow to pass down the design constraints to hierarchical sub blocks
  • Create Block / full chip level metal track plan including power grid.
  • Generate block/chip level static timing constraints.
  • Generate and Implement ECOs to fix timing, noise and EM IR violations.
  • Run Physical design verification flow at Block / full chip level and provide guidelines to fix LVS/DRC violations to COE owners
  • Participate in Methodology/flow development for chip integration which include correct by construction designs
  • Exploring methodology improvements for better power, performance , area and overall productivity

     
Job Requirements:  
  1. Master’s/Bachelor’s degree in Electrical/Electronics engineering with 4-8 years experience in semi-custom or PNR design
  2. Knowledge of and/or experience with industry standard PNR tools which include Cadence Innovus, Synopsys ICC/ICC2
  3. Knowledge of and/or experience with industry standard design and verification tools such as Virtuoso, PrimeTime and Calibre
  4. A good understanding of electrical, timing and reliability issues in deep sub micron circuit design.
  5. Strong debug skills
  6. Scripting experience using Perl, TCL, C-shell, Make and/or other scripting languages
  7. Knowledge and experience with basic Unix data management and job control
  8. Excellent written and oral communication skills

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