Our job listings have moved! Please update your bookmarks to our New Site and explore your next career opportunity.


Senior Design Engineer 1

📁
Design Engineering
📅
155332 Requisition #
Thanks for your interest in the Senior Design Engineer 1 position. Unfortunately this position has been closed but you can search our 228 open jobs by clicking here.
Your responsibilities include but are not limited to:
 
 
  • Block level place and route to design closure meeting timing, area and power constraints.
  • Develop full chip design methodologies and flow to pass down the design constraints to hierarchical sub blocks
  • Create Block / full chip level metal track plan including power grid.
  • Generate block/chip level static timing constraints.
  • Generate and Implement ECOs to fix timing, noise and EM IR violations.
  • Run Physical design verification flow at Block / full chip level and provide guidelines to fix LVS/DRC violations to COE owners
  • Participate in Methodology/flow development for chip integration which include correct by construction designs
  • Exploring methodology improvements for better power, performance , area and overall productivity

     
Job Requirements:  
  1. Master’s/Bachelor’s degree in Electrical/Electronics engineering with 4-8 years experience in semi-custom or PNR design
  2. Knowledge of and/or experience with industry standard PNR tools which include Cadence Innovus, Synopsys ICC/ICC2
  3. Knowledge of and/or experience with industry standard design and verification tools such as Virtuoso, PrimeTime and Calibre
  4. A good understanding of electrical, timing and reliability issues in deep sub micron circuit design.
  5. Strong debug skills
  6. Scripting experience using Perl, TCL, C-shell, Make and/or other scripting languages
  7. Knowledge and experience with basic Unix data management and job control
  8. Excellent written and oral communication skills

Previous Job Searches

Activity Feed

57906
Job shares through Xilinx
Someone applied to the Design Verification Engineer position as a result of a referral. 1 day ago
Someone applied to the Corporate Events Program Manager position as a result of a referral. 1 day ago
Someone applied to the Design Verification Engineer position as a result of a referral. 3 days ago
Someone applied to the FPGA IC Design Analysis Intern position as a result of a referral. 5 days ago
Someone applied to the IT Graduate position as a result of a referral. Jun 13, 2018

Similar Listings

Hyderabad, India, India

📁 Design Engineering

Requisition #: 154336

Hyderabad, India, India

📁 Design Engineering

Requisition #: 155158

Hyderabad, India, India

📁 Design Engineering

Requisition #: 153622

Equal Employment Statements

UNITED STATES: Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation. The information requested here is used only in compliance with US Federal laws and is not gathered for employment decisions. Responses are strictly voluntary, and any information provided will remain confidential. If you choose not to "self-identify", you will not be subject to any adverse treatment.

CANADA and EUROPE: Xilinx is an equal opportunities employer.

SINGAPORE and AUSTRALIA: Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to age, race, gender, religion, marital status and family responsibilities, disability or sexual orientation.

CHINA, HONG KONG, KOREA, PHILIPPINES and TAIWAN: Xilinx is an equal opportunity and affirmative action employer. Applicants and employees are treated throughout the employment process without regard to race, color, religion, national origin, citizenship, age, sex, marital status, ancestry, physical or mental disability, veteran status or sexual orientation.